Over the past several years rapid progress has been made in increasing the density of integrated circuits. The semiconductor industry has progressed from small scale integrated circuits to large scale integrated circuits and is currently on the threshold of very large scale integrated circuits. As the density of circuits fabricated on each chip on a wafer has increased, problems have arisen in attempting to provide interconnections between circuit elements. To take full advantage of increased circuit density, it is necessary to be able to make interconnections among the circuit elements in a high density manner. Generally with today's level of integration of circuits on a chip, interconnections cannot be made in a single level network of conductive material formed on the wafer. Instead, it is necessary to provide at least several levels of conductor networks on the wafer, each separated by an insulating layer through which contact windows or vias are formed, in order to distribute signals among circuits on the chip and to provide interconnection between individual conductor networks at various levels.
Prior art multilevel interconnect systems have generally utilized a straightforward approach of normal photoresist patterning and etching operations to construct successive layers of insulating material and conducting material (metal) to form an interconnect system. Windows are defined in the insulating material for allowing contacts between the circuit elements on wafer and the first metal layer, and between the respective metal layers in the successive multilevel arrangement. Metal layers are etched to form the predefined conduction paths of the network of the integrated circuit. However, because of process related design constraints inherently involved in this straightforward process, the multilevel interconnect systems which can be produced greatly limit the overall density of interconnection among the various layers. In addition, the yield and reliability of this interconnect system is generally poor because of its non-planar surface topology.
FIGS. 1, 2, and 3 in the attached drawings depict two common prior art multilayer interconnect systems. FIG. 1 is a plan view generally depicting the topographical layout of some of the various levels of metal conductor networks and contact windows in the two prior art multilevel interconnect systems depicted in cross-section in FIGS. 2 and 3. FIG. 2 depicts the cross-section through a multilayer conductor interconnect system which utilizes a straightforward process of forming successive layers of insulating material and metal on the integrated circuit wafer. FIG. 3 illustrates a modified prior art process which involves planarizing the layers of insulating material interposed between the metal layers.
FIGS. 1, 2, and 3 generally illustrate several of the limiting factors and problems involved in the multilevel interconnect systems of the prior art. These limitations and problems involve the large chip area and the steep metal step which is required for making a three-level interconnection between a substrate region such as region 11 in substrate 10 in FIGS. 2 and 3 and a third layer of metal 80 formed on the wafer. Because of the large area occupied by this three-level interconnect, other contact windows to the substrate 10 must be spaced an adequate distance from the adjacent three-level connection in order to provide sufficient electrical isolation between the connections. In addition, wherever it is desired to make a connection between two successive metal layers, it is necessary at each location to enlarge the path of the lower layer at that point in order to allow for mask alignment errors which may occur in carrying out the photomasking and etching operation utilized to provide the contact window in the overlying insulating layer. Furthermore, the overlying metal layer is required to have a large contact area in order to allow for tolerances in alignment of the photomask used to define the metal contact region with respect to the previously formed window in the underlying insulating layer. These allowances for misalignment of successive photomask and etching operations can best be understood from a description of successive process steps performed to build up the multilevel topology depicted in FIGS. 2 and 3.
Referring briefly to FIG. 2, substrate 10 generally designates a semiconductor wafer which has already been processed to fabricate a large number of individual integrated circuit chips. A substantial number of process steps have already been performed to provide a circuit formed of various diffused regions, such as regions 11 and 12, in the substrate 10. It should be understood that many junctions in the silicon substrate are not shown in the figures in order to make the explanation of this invention easier to understand. For purposes of illustration, FIG. 2 depicts a section of an integrated circuit which has been processed in a bipolar process in which the actual circuitry is fabricated in the substrate itself. It should be understood, however, that these multilevel conductor interconnect systems can also be readily adapted to conductor-insulator-semiconductor (CIS) integrated circuit technology. CIS technology involves not only the formation of diffused regions in the substrate but also the fabrication of a topological structure on the substrate consisting of insulating and conducting layers in order to create field effect device structures in the form of transistors and capacitors as well as other circuit elements such as resistors and the like.
After the wafer has been processed to the point that connections are required among various doped regions on the substrate 10, such as regions 11 and 12 depicted in FIG. 2, the first step in forming a multilevel interconnect system is to form an insulating layer 30 across the entire surface of the wafer. Insulating layer 30 is then patterned using a standard photomasking and etching operation to produce contact windows 31 and 32 corresponding to diffused regions 11 and 12. Because of the mask alignment errors which may occur between the separate photomasking operations which define the diffused regions 11 and 12 and the windows 31 and 32, the area of the contact windows 31 and 32 must be smaller than the surface area of the diffused regions 11 and 12. The required differential between these areas depends on the design rules of a particular production process which, in turn, depends on the accuracy of the photomasks and alignment equipment being utilized.
Once the windows 31 and 32 have been etched into insulating layer 30, the photoresist mask pattern overlying the insulating layer 30 is removed and a layer of conductive material, such as aluminum or an aluminum alloy, is deposited over the entire surface of the wafer. Then another photomasking and etching operation is performed to pattern the metal layer 40 into a network of conductor pathways and contact pads. As shown in FIGS. 1 and 2, the contact pads designated 41 and 42 in metal layer 40 are made substantially larger than the area of corresponding windows 31 and 32 which communicate with the surface of substrate 10. These large metal contact pads are provided to allow for misalignment of both the photomask used to pattern metal layer 40 and the photomask used to pattern underlying insulating layer 30 and also misalignment which may later occur for a third photomask used to pattern the overlying oxide layer 50 in order to provide another contact window for the second metal layer 60. Where contact is to be made to the substrate or between successive metal layers, an enlarged contact pad must be provided to assure that the metal will completely cover the window in the underlying oxide layer.
Metal contact pad 41 is also made larger than the window aperture 31 because the overlying contact window 51 in the next insulating layer 50 is formed larger than the underlying contact window 31 to decrease the steepness of the metal step formed as the next layer of metal is deposited on the wafer. Each succeeding contact window in overlying insulating layers 50 and 70 is made larger in order to reduce the steepness of the step in the metal layer formed thereat. As successive metal contact regions are built up, the areas of the metal contact regions, for example, regions 41, 61, and 81, progressively get larger to allow for misalignment in the photomasks used to create these structures. The large area of the chip occupied by these three-level metal contact points results in a low interconnect density which limits the density of circuitry that can be effectively created in the integrated circuit substrate itself.
Referring briefly to the contact pad 43 shown in FIGS. 1 and 2, it can also be seen that substantial chip area is consumed where a single level interconnection is being made. The narrow conductive path 42A must be broadened out to form contact pad 43 in order to provide for misregistration between contact window 52 and contact pad 43. Correspondingly, the size of metal contact pad 62 is substantially larger than window aperture 52 in order to provide for misregistration of the photomasks defining these two structures. This requirement for "undersized vias" or "small contact windows" with respect to large contact pads greatly reduces the density of the overall interconnect system. Moreover, despite the attempts to produce gradual slope in the metal steps employed in making a connection between three sequential metal layers such as shown in the lefthand portion of FIG. 2, the thinness of the metal layers in certain regions somtimes results in fracturing of the metal which in turn causes an open circuit condition and a defective chip. Accordingly, the overall production yield of an integrated circuit fabrication operation is adversely impacted by the problems involved in fabricating a multilevel interconnect system of this prior art type.
The prior art multilevel interconnect system depicted in FIG. 3 is a modified form type which shares the disadvantages of the approach depicted in FIG. 2 from the standpoint of the area occupied by the various interconnect points. In the process used to fabricate the structure depicted in FIG. 3, the various insulating layers 30, 50, and 70 are made planar to eliminate some of the metal steps in the system. This planarization may be performed using either a silicon dioxide reflow process which smooths out the surfaces of the silicon dioxide insulator layers or by utilizing a layer of silicon dioxide or polyimide initially dispensed onto the wafer in liquid form to fill in gaps in the underlying structure while providing a generally planar top surface. The process depicted in FIG. 3 does not improve the overall density of the multilevel interconnect system but does ameliorate some of the manufacturing yield problems by reducing the number of metal steps. As very large scale integration progresses, interconnect density of multilevel systems must be improved to take full advantage of increased circuit densities.
FIGS. 4 and 5 depict one approach to improving interconnect density in a multilevel interconnect system as disclosed in a co-pending and commonly assigned Chiang patent application Ser. No. 188,482, abandoned, "Integrated Circuit Multilevel Interconnect System and Method," and filed Sept. 18, 1980. As shown in FIG. 5, the cross-sectional topology of this improved multilevel conductor interconnect system generally involves a semiconductor wafer 100 and a multilevel conductor interconnect system 110 formed on the surface of wafer 100. Wafer 100 is a processed semiconductor wafer with the circuitry already formed therein. The wafer 100 generally depicted in FIG. 5 is exemplary of a wafer processed in accordance with some type of bipolar semiconductor process which involves fabricating the integrated circuit components in the wafer itself with little or no topologic structure built on the surface of the wafer.
The particular multilevel conductor interconnect pattern 110 depicted in FIG. 5 corresponds generally to the interconnect pattern shown in FIGS. 1, 2, and 3 systems in order to contrast the higher density of that interconnect system. As depicted in FIG. 5, multilevel conductor interconnect system 110 involves six planar composite layers of insulating and metal material grouped in three pairs (e.g., IA, IB forming a first pair). The three pairs of composite layers provide a three-level interconnect system. The first layer in each pair of layers generally is a contact window or via layer with the second layer comprising a patterned conductor interconnect network involving a plurality of conductor pathways extending between contact window locations which provide contact points to the semiconductor substrate or to an adjacent conductor interconnect level. Composite layer IA formed on substrate 100 consists of patterned regions of a first insulating material 120 which basically define contact windows for doped regions 101 and 102 in substrate 100. Conductive material sections 121A and 121B, which may be any metal or other conductor material typically used in the semiconductor industry, form contacts to the regions 101 and 102. Surrounding the metal contact regions 121A and 121B are small gap-filling regions of a second insulating material 122.
Each layer of interconnect system 110 generally has the same structural characteristics, i.e. it is a composite of two insulator materials and a conductive material. Thus, layer IB includes regions of a first insulator material 130 which generally define an interconnecting conductor network composed of conductors 131A, 131B, and 131C as outlined in FIG. 4. The gap-filling regions 132 of a second insulating material complete the structure of composite layer IB. Layer IIA is another window or via layer and illustrates the adaptability of the interconnect system of FIG. 5 to utilization of what are called "oversized vias", which simply means that the geometric area of the via or window is larger than the underlying conductor path. This is illustrated in FIG. 4 at the bottom righthand corner where it is seen that the metal region 141B lies within a window which is larger than the underlying segment of the conductor 131B and also larger than the segment of the overlying conductor 51B which metal contact region 141B interconnects. Contrasting this oversized via approach to the large contact pad, undersized via approach utilized in the systems as depicted in FIGS. 1 and 2, it will be readily appreciated that the oversized via approach provides a higher density of vias or windows and higher density of interconnect paths in each level of the interconnect system. FIG. 4 shows only some of the topography of the various conductor paths and windows or vias in the interconnect network 110 in order to demonstrate generally the arrangement of the various conductor regions without confusion of overlapping geometries.
While the multilevel interconnect system and method disclosed in the above-referenced copending Chiang patent application provides increased interconnect density and eliminates problems associated with steep metal steps, the process disclosed requires some carefully controlled etching steps. In one embodiment there is an etching operation in which an etch stop layer is not present underneath the layer being patterned. In another embodiment careful control of an etch back operation is required in order to maintain the planartopology of the individual composite layers as they are formed. In addition the system and method of the prior application is somewhat difficult to adapt to forming multilevel interconnect arrangements on top of processed wafers which already have an uneven topology involving hills and valleys due to an arrangement of insulating and/or conducting layers previously formed on the substrate.
Accordingly, it is the principal object of this invention to provide an improved plural layer conductor interconnect system.
More specifically, it is an object of this invention to provide a plural level conductor interconnect system having high interconnect density and adaptability to any wafer topology.
It is another object of this invention to provide a simplified process for forming an improved plural level conductor interconnect system.